Hierarchical multiprocessor system for video signal processing

verfasst von

Joerg Wilberg, Matthias Schoebinger, Peter Pirsch

Abstract

The architecture of a hierarchical multiprocessor (MP) system for videocoding is discussed. The topmost level of the proposed MP-system consists of identical, bus connected processing elements (PEs). A heterogeneous MIMD (multiple instruction multiple data) architecture is proposed for the PE. The PE contains a shared local memory and processing units, which are adapted to specific tasks. A strategy for optimizing the efficiency (defined by inverse area × processing time) at different levels of the hierarchy is proposed. This allows to realize an H.261 videocodec with only a few, if not a single PE. The efficiency of each PE can be increased, if multiple datablocks are processed concurrently within the PE (macropipelining). On the basis of a 1.0 μm CMOS technology a single PE (clock rate 50 MHz) can process the H.261 videocodec (except variable length coding and decoding) for CIF images at a frame rate of 18 Hz. Assuming an 0.6 μm CMOS technology, a single PE is expected to process frame rates of 30 Hz. A rough estimate of the silicon area for this technology is in the order of 100 mm².

Organisationseinheit(en)

Laboratorium f. Informationstechnologie

Typ

Aufsatz in Konferenzband

Seiten

1076-1087

Anzahl der Seiten

12

Publikationsdatum

1992

Publikationsstatus

Veröffentlicht

Peer-reviewed

Ja

ASJC Scopus Sachgebiete

Elektronische, optische und magnetische Materialien, Physik der kondensierten Materie, Angewandte Informatik, Angewandte Mathematik, Elektrotechnik und Elektronik